1. Field of the Invention
The present invention relates to electronic circuits. More specifically, the present invention relates to the design of a capacitance-measurement circuit.
2. Related Art
Accurate capacitance models are typically used during the process of designing high-performance integrated circuits. Critical design parameters, such as the delay through logic circuits, the bandwidth of analog circuits, and the power required for cross-chip communication largely depend on wire and device capacitance. Capacitance models often include a combination of physical equations, 2-dimensional or 3-dimensional field simulations, and/or measured capacitances. Typically, physical equations and measured capacitances are only available for a limited set of capacitance geometries. Other geometries are typically modeled using field simulations, which are calibrated using the physical equations and measured capacitances. Hence, precise capacitance measurements can greatly improve the field simulation parameters and can thus provide more accurate capacitance models for high-performance circuit design.
More precise capacitance measurements can also improve the effectiveness of “proximity communication.” In proximity communication, arrays of capacitive transmitters and receivers on semiconductor chips are used to provide inter-chip communication. When a first chip is situated face-to-face with a second chip, capacitive coupling between transmitter pads on the first chip and receiver pads on the second chip can be used to communicate signals between chips. However, to operate effectively capacitive coupling requires proper alignment between the transmitter pads and the receiver pads, both in a plane defined by the pads and in a direction perpendicular to the plane.
Misalignment between the transmitter pads and the receiver pads may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, satisfactory communication requires alignment such that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, limiting overall misalignment may improve communication performance between the chips and reduce power consumption. Therefore, in order to correct for misalignment between chips, accurate measurements of coupling capacitances are often necessary.
Unfortunately, existing capacitance-measurement techniques often suffer from limited sensitivity. For example, many techniques involve precise measurements of very small currents, which is becoming increasingly difficult because of the large amounts of transistor leakage current that arise as circuit dimensions continue to decrease. These leakage currents may cause problems when measuring the capacitances of wires in integrated circuits, which may be extremely small due to submicron dimensions of modern integrated circuit processes.
For example, in a 90-nanometer technology a wire may be only 150 nanometers wide and may have a capacitance smaller than a femtoFarad (fF). In order to measure to two significant digits, an accurate measurement technique would, therefore, require an attoFarad (aF) resolution, which may exceed the capability of existing capacitance-measurement techniques.
Hence, what is needed, therefore, is a capacitance-measurement technique that overcomes the problems listed above.